EmbeddedSystemsLab is intended to help Engineers, students and hobbies to learn FPGA by providing VHDL\Verilog courses & tutorials. We help to increase the learning curve by sharing over 10 years experience of FPGA design using VHDL and Verilog

Full Adder

In this VHDL project, VHDL code for full adder is presented. the Full Adder has 3 inputs A, B and Carry in and it has 2 outputs Sum S and...

N-bit Adder in VHDL

To create a structural adder circuit based on Full Adder, the best way is to use generate statement. This code represents the design of 8...

Understanding Flip Flops & Latches in VHDL

D Flip-Flops & Latches are the smallest storage elements in digital circuits. The D Flip Flop stores the value of the input D with the...

Multiplexer design in VHDL

The multiplexer is an essential digital circuit to select one of different inputs, structurally the 2x1 multiplexer circuit consists of 2...

HEX to seven segment decoder in VHDL

The seven segment display consists of 7 LED's which can be used to display number from 0 to 15 in hex format. There is two types of seven...

Free Multiplication & Division in VHDL

The Multipliers and Dividers usually consumes many hardware resources in your design and in a fully parallel design architecture you may...

Clock Division & down-sampling in VHDL

In many designs it is required to reduce the clock frequency of the main oscillator either for interfacing with low speed device or for...

Counter design in VHDL

This post will present the design of different types of counters in VHDL, up counter, up counter with load and up-down counter. A test...

Memory modeling in VHDL

Memory is an essential components in most FPGA designs, it is used for storing temporary data for processing, storing constant...

Memory initialization in VHDL

In this post we will illustrate different methods of memory initialization in VHDL, before reading this post it is recommended to read...

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