Full Adder
In this VHDL project, VHDL code for full adder is presented. the Full Adder has 3 inputs A, B and Carry in and it has 2 outputs Sum S and Carry out. The VHDL code for the adder is implemented by using structural model.
VHDL code for Full Adder :
Test Bench For Full Adder :
Simulation results :
I hope it is useful, please leave your questions or suggestions if you have any