Free Multiplication & Division in VHDL
The Multipliers and Dividers usually consumes many hardware resources in your design and in a fully parallel design architecture you may end up running out of resources, however in many cases multiplication and addition can be performed without consuming any extra logic elements this is called free multiplication and free division.
The free Multiplication & division can be performed for dividing by constant or multiplying by constant it is based on the fact that a single left shift is equivalent to multiplication by 2, and a single right shift is equivalent to division by 2.
Example 1 Multiplication:
for multiplication by constant 2 in VHDL you may just write the following in your code :
result(7 downto 0) <= data(3 downto 0) * "0010";
However this will infer the following circuit in your FPGA
but you can also perform the exact same function without consuming these logic elements in your FPGA as follow
result(4 downto 0) <= data(3 downto 0) & '0';
assume that data is equal to "0011" which is 3, then the result is "00110" which is 6, here no multiplier is inferred in hardware, only single bit shift. By the same way a 2 bit shift to the left will result in multiplication by 4 and a 3 bit shift will result in multiplication by 8.
another multiplication by constants can be performed by using addition
Example 2 Multiplication:
Multiply by constant 5 :
result(5 downto 0) <= (data(3 downto 0) & "00") + data;
again for input value of "0011" the result will be "001100" + "0011" = "001111" = 15
Therefore it is suitable to perform free multiplication with a constant number to the base 2 by simply performing a left shift, and it is suitable to perform multiplications with other numbers by performing the left shift and adder
Example 3 Multiplication & Division :
Similar to free multiplication, a single shift to the right will result in divide by 2, and a 2 left shift will result in divide by 4 and so on. assume we would like to calculate the 0.75 of a binary number N in a design, this can be performed with the least amount of logic utilization as follow :
(3 x N) / 4 = 2N/4 + N/4
2N/4 = shift N 1 bit to the right
N/4 = shift N 2 bits to the right
assume that N = 96 = "01100000", the result will be "00110000" + "00011000" = "01001000" which is 72, this operation will be implemented on FPGA without using any Multiplier or Divider circuits