Memory modeling in VHDL
Memory is an essential components in most FPGA designs, it is used for storing temporary data for processing, storing constant coefficients and even for transferring data between 2 different clock domains.
In this post we are going to illustrate the VHDL design of different memory models, including single port RAM, dual port RAM and ROM. To describe a memory in VHDL, the first step is to create an array data type with a number of locations equal to the required memory depth, the size of each element in the defined array should be equal to the required memory width.
different memory types can then be designed by changing the method of accessing the defined array for reading and writing as follow:
Note : the address data type must be converted from std_logic_vector to integer to be able to define the required index of the array either for read or write
1- single port RAM
2- Dual port RAM
3- Dual port Ram with separate read write clocks
4- ROM
In the next post we shall illustrate the different methods of initializing the memory contents in VHDL