Clock Division & down-sampling in VHDL
In many designs it is required to reduce the clock frequency of the main oscillator either for interfacing with low speed device or for performing down-sampling. The clock frequency can be divided by 2 simply by using a D flip flop and inverter as shown in the following figure
but for higher division factor the circuit becomes more complex, it requires a free running counter and a comparator. the counter must count continuously to a number equal to n which results in the required clock period according to the following equation :
Trequired = n x Tclk
The comparator output is equal to 1 when the counter value is higher than n / 2 and it represents the required clock
The VHDL code for the clock divider is :
The test bench for the clock divider :
Simulation results:
