Decoder design in Verilog

Decoder is one of the main combinational components in digital circuits that converts binary information from the n coded inputs to a maximum of 2^n unique outputs. Decoders are mainly used in memory address decoding and data demultiplexing.

The following verilog codes represents 2 different coding styles for implementing 4x16 decoder in verilog, a test bench is also included, these codes can be easily modified to implement different decoders.

1- 4x16 Decoder using assign statement :

2- 4x16 Decoder using case statement :

3- Test bench for 4x16 decoder :

Simulation Results :

#decoder #verilog