Full Adder in Verilog

The Full Adder circuit performs the addition of two input bits A & B and and input carry, and the result is the sum S and a carry out. The circit consists of 2 AND gates, 2 XOR gates and 1 OR gate as shown in the following figure.

The Full adder is the basic building block for Adders and subtractors circuits in digital circuits, the Verilog code for Full Adder in addition to test bench is presented in this post. The internal connecting wires wire1, wire2 and wire3 are defined as wire data type in the verilog code and the logic gates are defined using verilog functions

Verilog code for Full Adder :

Verilog Test Bench for Full Adder :

Simulation results :

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