Xilinx XADC Part2 : Multiple analog inputs

In this project the Xilinx XADC will be used to sample 3 external analog input signals for this purpose the XADC will be configured to operate in the channel sequencer mode to continually sample the 3 analog channels and store the results in the status registers. The Basys 3 board will be used in the project

1- In the block design add XADC IP and double click on it to open the Re-customize GUI.

2- In the startup channel selection choose Channel Sequencer to allow the XADC to sample multi channels in sequence.

3- The Basys 3 board gives access to VAUX6, VAUX7, VAUX14 and VAUX15 channels of the XADC using the JXADC PMOD, therefore channel VAUX4, VAUX7 and VAUX14 will be checked in the channel sequencer tab the press OK to finish.

4- The right click on each of the VAUX channels on the IP and make it external.

5- A slice IP is used to extract the 12 most significant bits of the output

6- connect eoc_out port to den_in input and connect dwe_en and di_in to constant 0

7- since the data for the 3 channels will be available on the same XADC output pot, the following VHDL code was written to demultiplex the XADC output into 3 separate channels, the code consists of a counter that counts continuesly from 0 to 2 to be used as 3 state sequence, during each state the address is applied to the XADC and data is read from it.

8- right click on the VHDL file in the sources window and choose Add Module to Block Design to add the VHDL code as a block in the block design.

9- connect the output from the slice IP to the input of the demultiplexer block, also connect the 3 outputs of the demultiplexer to the ila as data and connect the eoc_out as a trigger to the ila, the final block design should look like the following figure.

10 - the 3 analog outputs of the 3 phase generator project are used as test input

11- The following figure shows the sampled signals using the XADC