Tutorial 2 Part2 : Using ZedBoard Switches & LEDs
Introduction
In this tutorial we are going to do exactly the same function of tutorial 2 part1 but in this tutorial only PL will be used, we will learn how to create a VHDL code and adding user constraints.
Step1: Create new project using Vivado IDE
Create new project with the name of Zedboard_tutorial2_p2
Step2: Create New Source file
1- Click on the Add Sources icon in the Flow Navigator under Project Manager
2- Select Add or create design sources and click Next.
3- Click on create file, then in the Create Source File window choose the File type : VHDL and in File Name field write ByPass, then click ok, then click finish.
4- In the Define Module window write se and led in the Port Name with sw direction in and led out, check the Bus box for both and set the MSB to 7 so that it looks exactly like figure 4 this creates an 8 bit input bus called sw and 8 bit output bus called led.
5- Double click on the Bypass file in the source window and in line 43 write the following led <= sw; the code will look like figure 5. Now you have connected the 8 bit bus sw to the 8 bit bus led
Step 3 : create pin assignment
In the previous tutorials, we didn’t set any pin assignment for the Zedboard in the Vivado project, which is because the design assistance did it automatically when we click , but now we are using VHDL only and there is no design assistance option so we need to do this job.
For every Board there is a file called master constraints file, it includes the pin assignment for all the Pins of the FPGA on the board, all we need to do is to include this file in our project and rename it with the name of the ports in our VHDL file
Note: when renaming the pins in the constraints file take care because it is case sensitive.
1- The master constraints file for the Zedboard is called zedboard_master_XDC_RevC_D_v2.xdc, click on the Add Sources icon in the Flow Navigator under Project Manager as shown in figure 1, then choose add or create constraints which is the first option and click next. Now click on Add Files and add the zedboard_master_XDC_RevC_D_v2.xdc file the file should be added as shown in following figure.
Check the Copy constraints file into project box so that you can make modifications on the copy of the file not the main one then click finish.
2- Expand the constraints folder in the source window and double click on the zedboardfile, the file should open to the left as shown in following figure.
Now we need to rename the pin constraints of the Switches and the LEDS to be the name as the Buses in our VHDL code, scroll down the file until you find
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ----------------------------------------------------------------------------
This indicates the start of the pin constraints for the LEDs, here we can see that they used the Name LD0, LD1, … LD8 for the pin, this discrete names should be modified to the bus name led ( which is our Bus name for the leds in the vhdl file), rename all LD with led and take care that it is case senstive, it should look like following figure.
3- By the same way scroll the constrains file until you find
# ----------------------------------------------------------------------------
# User DIP Switches - Bank 35
# ----------------------------------------------------------------------------
The commented section indicates the start of the pin assignment for the switches, rename the discrete names SW0, SW1, … SW8 with Bus name sw( the bus name we use for the switches in our VHDL file). It should look like figure 8.
Click on Files-> Save All files.
Step4: Programming the Zedboard using Bitstream
In this project there is no processing system, therefore there is no need to export files to SDK or write a C application and the Zedboard will be programmed only with the Bitstream from the Vivado.
1- In the flow navigator, click on generate bitstream or click on flow->generate bitstream. During this step the tool creates a bit file for programming the PL of the ZYNQ. During the generation a warning message should appear telling you that not all constrained pins are used by your design, click ok.
2- When the Bitstream Generation Completed window pop up, choose open hardware manager and click ok.
3- In the hardware Manager click on open target then auto connect to connect to the Zedboard through jtag
4- Click on program device and choose the connected device xc7020 then clock program.
