Structural N-bit Adder/Subtractor using Generate statement in Verilog
Structural Adder/Subtractor can be designed in verilog based on Full Adder, this is done by instantiating N modules of the full adder. Generate statement in Verilog can help to perform this without having to write instantiation code for the full adder N times.
To Perform subtraction using the same adder circuit, the sign of the second operator must be changed, this means that the Two's complement of the second operator must be calculated before applying it as an input to the Adder circuit this is done using a multiplexer. since the two's complement is calculated by inverting the binary word and adding 1 to it, all we need to do is to set the input carry to 1 and invert the input to perform the subtraction, the final circuit is shown in the following figure
Verilog Code for Adder/Subtractor :
Test Bench :
simulation results :
