EGC Denoising Filter in VHDL

Introduction

An FIR filter is a filter whose impulse response is of finite duration; as it lasts for exactly “N+1” samples before it returns back to zero, where N is the order of the filter[1].

This project represents the design of Low pass least-square FIR filter for removing signal noise with a sampling frequency of 360 HZ and Order 10 (tap : 11).

The filter is design can be done using different methods, including computer added software such as Matlab, this is done in order to calculate the filter coefficients. After that filter implementation can be done by designing a VHDL code for realizing the filter using the coefficients calculated.

Design

The FIR filter consists of 11 pipeline registers denoted as That the output of each register is the input of the following as shown in figure 1, the output of each element D is multiplied by coefficient b which is previously calculated.

Therefore the filter design requires, 11 registers, 11 multipliers and 11 adders.

These elements are defined as array types in VHDL as below

The calculated coefficients are defined as constants in the VHDL code as follow

The pipeline operations is done by feeding the output of each register to a second one this is done in a process as a word shift operation

The value of each D register is multiplied by its corresponding coefficient value.

Finally the product is summed to create the final output of the filter

Testing and verification

In order to make simulations a test bench is written which use external text file to generate the input signals for the filter then the output is seen in the Modelsim’s wave window

Test bench

The test bench to test the circuit is done by using the text.io library to be able to read the values from external text file and use it as an input to the filter, the following figure shows the process used in test bench to read the text file and set it as filter input

Simulation waveform

After running the resulting simulations shows that the filter is performing the required function and is functioning correctly the following figure shows the filter input as the top and the filter output at the bottom using Modelsim simulator wave form

codes and test bench are all available for free

https://www.youtube.com/watch?v=nKD6CmyN6bs

#FPGA #VHDL #Altera #Filter #FIR