VHDL data type conversion

Although std_logic_vector and std_logic are the most common data types used in synthesizable VHDL designs, but also another different data types can be used in the same VHDL code. Different data types are used either for increasing the code readability or for the advantage of using sum functions associated with some data types.

Library numeric_std contains the required conversion functions between different data types. actually conversion can be classified as type casting and type conversion.

Data type conversion can be done either by type casting or using conversion function.

Type casting :

Type casting is done between data vectors of different types

1. Convert signed\unsigned to std_logic_vector

Std_logic_vector(data);

2. Convert std_logic_vector to signed\unsigned

signed(data);

unsigned(data);

Type conversion :

conversion functions are used for conversion between integers and bit vectors

1. Convert singed\unsigned to integer :

To_integer(data);

2. Convert integer to std_logic_vector

To_integer(unsigned(data);

3. Convert integer to singed\unsigned :

To_signed(data, data’length);

To_unsigned(data, data’length);

The following chart summarize the available type conversion and type casting using numeric_std library

The following VHDL code shows an example of type conversion and type casting in VHDL