VHDL Data types
The VHDL use different data types, these data types can be divided into two main categories, synthesizable data types and non-synthesizable data types.
1-Synthesizable data-types:
The synthesizable data types are those that can be used to define single data bit or data bus for real hardware implementation, the synthesizable data types are used to organize the code and/or define the scope of the arithmetic operations performed by the design (i.e signed, unsigned operations).
In the previous post we defined the VHDL code structure and we used a NAND gate description code as an example, the data type declared in the entity for the ports was STD_LOGIC, the STD_LOGIC data type in VHDL is used to define a single data bit or data bus that can hold 9 different values, these values are:
'U', Uninitialized (the default)
‘0’, Forcing 0
’1’, Forcing 1
’X’, Forcing unknown
’Z’, High impedance
’W’, Weak unknown
’L’, Weak low
’H’, Weak high
’-’, Don’t care
To define a data bus the STD_LOGIC_VECTOR is used and it must have a range and bit order, for example, an 8 bit data bus ordered from MSB to LSB is defined as
Signal Databus1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
If we want to change the bit order from LSB to MSB it should be defined as
Signal Databus2 : STD_LOGIC_VECTOR(0 TO 7);
And it is also perfectly legal to say
Databus2 <= Databus1;
As they both have the same number of elements.
In real hardware implementation the STD_LOGIC or STD_LOGIC_VECTOR hold only 3 values logic level ‘0’, logic level ‘1’and ‘Z’, the rest of the 9 values are used only for simulation purpose to help the designer to debug his code, for example, if a signal is not initialized, it would show ‘U’ in the simulation indicating that the designer forgot to initialize it, but in real hardware it will carry the level ‘0’.
It is not allowed to perform arithmetic operations on a STD_LOGIC_VECTOR signals, unless the sign of the operations are previously defined, this is done by declaring the following library in the VHDL code libraries section:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
or
use IEEE.STD_LOGIC_SIGNED.ALL;
Example:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ADDER is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
SUM : out STD_LOGIC_VECTOR (3 downto 0));
end ADDER;
architecture Behavioral of ADDER is
begin
SUM <= A + B;
end Behavioral;
Another method is to define the library
use IEEE.STD_LOGIC_ARITH.all;
And in that case the STD_LOGIC_VECTOR data type can be replaced by the data type SIGNED or UNSIGNED which are basically STD_LOGIC_VECTOR data types with a predefined sign for arithmetic operations.
Example:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
entity ADDER is
Port ( A : in UNSIGNED (3 downto 0);
B : in UNSIGNED (3 downto 0);
SUM : out UNSIGNED (3 downto 0));
end ADDER;
architecture Behavioral of ADDER is
begin
SUM <= A + B;
end Behavioral;
The Bit and BIT_VECTOR data types can also be used to express a single data bit and data bus, the main difference between bit and std_logic is that it can hold only 2 different values
‘0’, Forcing 0
’1’, Forcing 1
This is not good for simulation purpose however the bit_vector data type allow the use of predefined functions such as shifting functions:
SRL shift right logic
SLL shift left logic
SRA shift right arithmetic
SRL shift right arithmetic
ROR rotate right
ROL rotate left
In addition to resize function, to take the advantage of using these function, signals can be declared as bit_vector then converted back to std_logic_vector, data type conversion will be discussed in more details in the next post.