Signals versus Variables

There is two main differences between signals and variables in VHDL language, the first difference is that the Signal is global this means it can be read or assigned from any part of the VHDL code while the Variable is local to the process.

The second difference is that the variable value is changed immediately this is illustrated with the following example

Process(clk)

Variable : Var1, Var2, Var3 : std_logic;

Begin

If rising_edge(clk)then

Sig1 <= data_in;

Sig2 <= Sig1;

Var1 := data_in;

Var2 <= Var1;

End if;

End process;